1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more specifically, to a vertical MOSFET having a gate trench structure and a method of manufacturing the same.
2. Description of Related Art
There is a vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) having a polysilicon electrode formed in a trench, which is formed in a surface of a silicon substrate. This is called gate trench structure. When an N-type FET having gate trench structure turns ON, current flows from a drain in a rear surface side of the silicon substrate to a source in a front surface side along with a channel part, which is formed on a surface opposed to a gate polysilicon electrode in a trench side surface.
In order to decrease a drain-source resistance in the vertical MOSFET, the impurity concentration of the silicon substrate (or epitaxial layer formed on the silicon substrate) in which the current flows can be increased. However, when the impurity concentration of the silicon substrate is increased for low ON resistance, a depletion region hardly extends to the silicon substrate and the electric field concentration readily occurs. As a result, a drain-source breakdown voltage (BVdss) becomes lower. According to a related vertical MOSFET, the drain-source breakdown voltage (BVdss) decreases when the ON resistance is to be decreased, as there is a trade-off relationship between them.
FIG. 14 is a cross sectional view showing a configuration of a vertical MOSFET having a trench gate structure according to a related art. A low-concentrated epitaxial layer 5 is formed on a highly-concentrated substrate 6. A source layer 2 and a base layer 3 are formed inside the low-concentrated epitaxial layer 5. A trench is formed in the low-concentrated epitaxial layer 5 with etching process or the like. A gate layer 1 and a gate oxide film 4 are formed inside the trench. The base layer 3 is formed in a part opposed to a trench gate side wall. In the related semiconductor device, the ON resistance is made lower by decreasing the film thickness of the low-concentrated epitaxial layer 5 or by increasing the impurity concentration.
FIG. 15 is a cross sectional view showing a vertical MOSFET having a gate trench structure disclosed in Japanese Unexamined Patent Application Publication No. 11-177086. In this vertical MOSFET, an island-shaped highly-concentrated region 7 is formed below the gate layer 1. The same components as those of FIG. 14 are denoted by identical reference symbols, and description thereof will be omitted. The island-shaped highly-concentrated region 7 is formed in the low-concentrated epitaxial layer 5 in a way that it is not formed immediately below a channel layer 3a formed in the base layer 3.